? semiconductor components industries, llc, 2003 october, 2003 ? rev. 8 1 publication order number: an1568/d an1568/d interfacing between lvds and ecl prepared by: paul lee logic applications engineer on semiconductor introduction recent growth in high?speed data transmission between high?speed ics demand more bandwidth than ever before while still maintaining high performance, low power consumption and good noise immunity. emitter coupled logic (ecl) recognized the challenge and provided high performance and good noise immune devices. ecl migrated toward low voltages to reduce the power consumption and to keep up with current technology trends by offering 3.3 v and 2.5 v low voltage ecl (lvecl) devices. lvds (low voltage differential signaling) technology also addresses the needs of current high performance applications. lvds as specified in ansi/tia/eia?644 by data transmission interface committee tr30.2 and ieee 1596.3 sci?lvds by ieee scalable coherent interface standard (sci) is a high speed, low power interface that is a solution in many application areas. lvds provides an output swing of 250 mv to 400 mv with a dc of fset of 1.2 v. external resistor components are required for board?to?board data transfer or clock distribution. lvecl and lvds are both differential voltage signals, but with different output amplitude and offset. the purpose of this documentation is to show the interfacing between lvecl and lvds. in addition, it gives interface recommendations to and from 5.0 v supplied pecl devices and negative supplied ecl or necl ecl levels today's applications typically use ecl devices in the pecl mode. pecl (positive ecl) is nothing more than supplying any ecl device with a positive power supply (v cc = +5.0 v, v ee = 0 v). in addition, ecl uses dif ferential data transmission technology, which results in better noise immunity. since the common mode noise is coupled onto the differential interconnect, it will be seen as a common mode modulation and will be rejected. with the trend towards low voltage systems, a new generation of ecl circuitry has been developed. the low voltage necl (lvnecl) devices work using negative 3.3 v or 2.5 v power supply, or more popular positive power supplies, v cc = +3.3 v or +2.5 v and v ee = gnd as lvpecl. lvecl maintains 750 mv output swing with a 0.9 v offset from v cc , which makes them ideal as peripheral components. the temperature compensated (100el, 100lvel, 100ep, 100lvep) output dc levels for the different supply levels are shown in table 1. ecl outputs are designed as an open emitter, requiring a dc path to a more negative supply than v ol . (see and8020 for ecl termination information). ecl standard dc input levels are also relative to v cc . many devices are available with voltage input high common mode range (v ihcmr ). these differential inputs allow processing signals with small v inppmin (down to 200 mv, 150 mv or even 50 mv signal levels) within an appropriate offset range. the v ihcmr ranges of ecl devices are listed in each respective data sheets. application note http://onsemi.com
an1568/d http://onsemi.com 2 table 1. mc100exxx/mc100elxxx/lvelxxx/epxxx/lvepxxx (t a = 0 c to +85 c) symbol parameter 2.5 v lvpecl (note 1) 3.3 v lvpecl (note 1) 5.0 v pecl (note 1) necl unit v cc positive supply voltage +2.5 +3.3 +5 gnd v v ee negative supply voltage gnd gnd gnd ?5.2, ?4.5, ?3.3 or ?2.5 v v oh maximum output high level 1.680 2.480 4.180 ?0.820 v v oh typical output high level 1.555 2.355 4.055 ?0.945 v v oh minimum output high level 1.430 2.230 3.930 ?1.070 v v ol maximum output low level 0.880 1.680 3.380 ?1.620 v v ol typical output low level 0.755 1.555 3.255 ?1.745 v v ol minimum output low level 0.630 1.430 3.130 ?1.870 v 1. all levels vary 1:1 with v cc and loaded with 50 to v cc ? 2.0 v. lvds levels as the name indicates, the lvds main attribute is the low voltage amplitude levels compared to other data transmission standards, as shown in figure 1. the lvds specification states 250 mv to 400 mv output swing for driver/transmitter (v outpp ). the low voltage swing levels result in low power consumption while maintaining high performance levels required by most users. in addition, lvds uses differential data transmission technology equivalent to ecl. furthermore, lvds technology is not dependent on specific power supply levels like ecl technology. this signifies an easy migration path to lower supply voltages such as 3.3 v, 2.5 v, or lower voltages while still maintaining the same signaling levels and high performance. on semiconductor currently provides a 2.5 v 1:5 dual differential lvds clock driver/receiver (mc100ep210s). figure 1. comparison of output voltage levels standards (figure not to scale) pecl 3.3 v lvpecl necl/lvnecl lvds 2.5 v lvpecl 3.3 v lvttl/lvcmos signal voltage lvds require a 100 load resistor between the differential outputs to generate the differential output voltage (v od ) with a maximum current of 2.5 ma flowing through the load resistor. this load resistor will terminate the 50 controlled characteristic impedance line, which prevent reflections and reduces unwanted electromagnetic emission (figure 2). figure 2. lvds output definition lvds z = 50 z = 50 100 lvds receivers require 200 mv minimum input swing within the input voltage range of 0 v to 2.4 v and can tolerate a minimum of 1.0 v ground shift between the driver's ground and the receiver's ground, since lvds receivers have a typical driver offset voltage of 1.2 v. the common mode range of the lvds receiver is 0.2 v to 2.2 v, and the recommended lvds receiver input voltage range is from 0 v to 2.4 v. common mode range of l vds is similar to the theory of voltage input high common mode range (v ihcmr ) of ecl devices. currently more lvds standards are being developed as lvds technology gains in popularity. blvds bus lvds (blvds) was developed for multipoint applications. this standard is targeted at heavily loaded back planes, which reduces the impedance of the transmission line by 50% or more. by providing increased drive current, the double termination seen by the driver will be compensated. m?lvds tia tr30.2 standards group is developing another multipoint lvds application called multipoint lvds (m?lvds). the maximum data rate is 500 mbps.
an1568/d http://onsemi.com 3 glvds and slvs ground referenced lvds (glvds) is similar to lvds except the driver output voltage offset is nearer to ground. the advantage of glvds is the use of very low power supply voltages (0.5 v). similar standard to glvds is slvs (scalable low?voltage signaling for 400 mv) by jedec. the interface is terminated to ground with 400mv swing and a minimum supply voltage of 0.8 v. lvdm lvdm is designed for double 100 ?terminated applications. the driver's output current is two times the standard lvds, thus producing lvds characteristic levels. interfacing common mode range inputs are capable of processing signals with 150 mv to 400 mv amplitude. the ecl input processes signals up to 1.0 v amplitude. the dc voltage levels should be within the voltage input high common mode range (v ihcmr ). to interface between these two voltage levels, capacitive coupling can be used. only clock or coded signals should be capacitively coupled. a capacitive coupling of nrz signals will cause problems, which can require a passive or active interfacing. table 2. lvds levels lvds specification blvds specification m?lvds specification glvds specification lvdm specification symbol parameter min max min max min max min max min max unit condition transmitter v pp output differen- tial voltage 250 400 240 500 480 650 150 500 247 454 mv v os output offset voltage 1125 1275 1225 1375 300 2100 75 250 1.125 mv r l load resistor 100 27 50 50 internal to rx 50 i od output differen- tial current 2.5 4.5 9 17 9 13 adjustable 6 ma receiver input voltage range 0 2400 0 2400 ?1000 3800 ?500 1000 0 2400 mv v gpd < 950 mv (note 2) differential high input threshold +100 +100 +50 +100 +100 mv v gpd < 950 mv (note 2) differential low input threshold ?100 ?100 ?50 ?100 ?100 mv v gpd < 950 mv (note 2) 2. vgpd is the voltage of ground potential delta across or between boards.
an1568/d http://onsemi.com 4 capacitive coupling lvds to ecl capacitive coupling lvds to ecl using v bb several ecl devices provide an externally accessible v bb (v bb v cc 1.3v) reference voltage. this ecl reference voltage can be used for differential capacitive coupling. the 10 nf capacitor can be used to decouple v bb to gnd. (figure 3) figure 3. capacitive coupling lvds to ecl using v bb lvds z = 50 z = 50 100 ecl 1 k 1 k v bb 10 nf 10 pf 10 pf capacitive coupling lvds to ecl with external biasing if v bb reference voltage is not available, equivalent dc voltage can be generated using a resistor divider network. the resistor values depend on v cc and v ee voltages (table 3). stability is enhanced during null signal conditions if a 50 mv differential voltage is maintained between the divider networks. (figure 4) table 3. examples: v cc = gnd v ee = ?5.0 v r1 = 1.2 k r2 = 3.4 k v cc = gnd v ee = ?3.3 v r1 = 680 r2 = 1.0 k v cc = gnd v ee = ?2.5 v r1 = 100 r2 = 90 figure 4. capacitive coupling lvds to ecl with external biasing lvds z = 50 z = 50 100 ecl r2 r2 r1 10 pf 10 pf r1 v cc v ee in the layout for both interfaces, the resistors and the capacitors should be located as close as possible to the ecl input to insure reduced reflection and increased signal integrity. capacitive coupling ecl to lvds the ecl output requires a dc current path to v ee ; therefore, the pulldown termination resistors, r t , are connected to v ee . the thevenin resistor pair represent the termination of the transmission line z = r1 || r2 and generates an appropriate dc offset level of 1.2 v. (figure 5) figure 5. capacitive coupling ecl to lvds z = 50 z = 50 ecl r t r t r1 130 10 pf 10 pf r1 130 3.3 v v ee r2 80 r2 80 lvds an example of capacitive coupled lvpecl (eclinps plus ? device) to lvds is shown below. (figure 6) figure 6. capacitive coupling lvpecl to lvds r2 43 lvpecl r1 237 r1 237 r3 3.9 k r3 3.9 k 3.3 v r4 2 k r4 2 k lvds 3.3 v 2.5 v or 3.3 v r2 43 10 pf 10 pf capacitive coupling ecl to lvds using v os reference voltage some lvds devices supply external offset reference voltage (v os ), which can be used for capacitive coupling. when the transmission line is very short, a parallel
an1568/d http://onsemi.com 5 termination should be used and placed as close as possible to the coupling capacitors. (figure 7) figure 7. capacitive coupling ecl to lvds using v os reference voltage z = 50 z = 50 ecl 1 k 1 k 100 k v os = 1.2 v 10 pf 10 pf 3.3 v 50 50 v tt lvds direct interfacing interfacing from 2.5 v lvpecl to lvds provided that the lvds receiver can tolerate large input voltage peak to peak amplitude, 2.5 v lvpecl can be directly interfaced to lvds receiver using proper ecl termination. 2.5 v lvpecl will be able to drive lvds receiver with and without internal 100 termination resistor. (see figures 8, 9 and 10). figure 8. interfacing 2.5 v lvpecl to lvds with external 100 termination resistor 100 lvpecl 2.5 v v cc r t r t lvds z o z o figure 9. interfacing 2.5 v lvpecl to lvds with internal 100 termination resistor 100 lvpecl 2.5 v v cc r t r t lvds z o z o figure 10. pspice simulation levels of 2.5v lvpecl to lvds interface with example resistor values 1.50 v 0.78 v 720 mv lvds input 2.5 v lvpecl output where r t = 75 furthermore, sreies termination can be used to reduce the amplitude of the signal as described in and8020 application note, by placing r s resistor between the driver and the transmission line. (see figures 11, 12 and 13). figure 11. interfacing 2.5 v lvpecl to lvds with series r s and external 100 termination resistor 100 lvpecl 2.5 v v cc r t r t lvds z o z o r s r s
an1568/d http://onsemi.com 6 figure 12. interfacing 2.5 v lvpecl to lvds with series r s and internal 100 termination resistor 100 lvpecl 2.5 v v cc r t r t lvds z o z o r s r s figure 13. pspice simulation levels of 2.5v lvpecl to lvds interface with series r s resistor 1.30 v 0.87 v 430 mv lvds input 2.5 v lvpecl output where r t = 75 r s = 43 interfacing from 3.3 v lvpecl to lvds since the output levels v oh and v ol of 3.3 v lvpecl are more positive than the input range of lvds receiver, special interface is required. (see figures 14 and 15). furthermore, the open emitter design of the ecl output structure need proper termination, which can be incorporated with the resistor divider network to generate a proper lvds dc levels (eq. 1). r 1 r 2 r t (eq. 1) the resistor divider network will divide the output common mode voltage of lvpecl (v cm (lvpecl)) to input common mode voltage of lvds (v cm (lvds)). r 2 r 1 r 2 v cm (lvds) v cm (lvpecl) (eq. 2) where: r t = termination resistor v cm (lvpecl) = common mode voltage v cm (lvds) = common mode voltage 3.3 v lvpecl will be able to drive lvds receiver with and without internal 100 termination resistor. the above equations may give non?standard resistor values and when choosing resistors off the shelf, to avoid cutoff condition under worst?case scenario. figure 14. interfacing 3.3 v lvpecl to lvds lvpecl lvds 3.3 v v cc r1 r1 r2 r2 z o z o z o z o 100 figure 15. interfacing lvpecl to lvds with internal 100 termination resistor lvpecl lvds 3.3 v v cc r1 r1 r2 r2 100 z o z o z o z o examples: for 50 controlled impedance, the resistor values for 3.3v lvpecl converted to lvds voltage levels are as follows: r 1 = 55 r 2 = 95 r t = 150 v cm (lvpecl) = 1.9 v v cm (lvds) = 1.2 v
an1568/d http://onsemi.com 7 figure 16. pspice simulated voltage levels of 3.3 v lvpecl to lvds interface with example resistor values 1.07 v 1.39 v 2.37 v 1.52 v 850 mv 320 mv lvds 3.3 v lvpecl v cm (lvpecl) v cm (lvds) interfacing from lvds to lvpecl the input common mode range of the low voltage ecl line receivers are wide enough to process lvds signals. (figure 17) figure 17. interfacing lvds to lvpecl lvds z = 50 z = 50 100 lvpecl 3.3 v 2.5 v or 3.3 v this direct interface is possible for all ecl devices with sufficiently low minimum differential input high common mode range inputs. a differentially operated receiver's v ihcmr minimum must be 1.2 v or less (see device data sheet). table 4. lvds input compatible devices ep14 lvep210s lvel37 el56 ep809 lve222 lvel39 el91 lvep11 lvel05 lvel40 sg11 lvep14 lvel11 lvel51 sg14 lvep16 lvel13 lvel56 sg16 lvep17 lvel14 lvel92 sg16m lvep34 lvel16 el13 sg16vs lvep56 lvel17 el14 sg53a lvep91 lvel29 el17 sg72a lvep111 lvel32 el29 sg86a lvep210 lvel33 el39 sg111 interfacing from pecl to lvds since the output levels v oh and v ol of 5 v pecl are more positive than the input range of lvds receiver, special interface is required. (see figure 18). furthermore, the open emitter design of the ecl output structure need proper termination, which can be incorporated with the resistor divider network to generate a proper lvds dc levels (eq. 3). r 1 r 2 r t (eq. 3) the resistor divider network will divide the output common mode voltage of pecl (v cm (pecl)) to input common mode voltage of lvds (v cm (lvds)). r 2 r 1 r 2 v cm (lvds) v cm (pecl) (eq. 4) where: r t = termination resistor v cm (pecl) = common mode voltage v cm (lvds) = common mode voltage the above equations may give nonestandard resistor values and when choosing resistors off the shelf, to avoid cutoff condition under worst?case scenario. figure 18. interfacing 5 v pecl to lvds pecl lvds 5 v v cc r1 r1 r2 r2 z o z o z o z o examples: for 50 controlled impedance, the resistor values for 5v pecl converted to lvds voltage levels are as follows: r 1 = 134 r 2 = 66 r t = 200 v cm (pecl) = 3.65 v v cm (lvds) = 1.2 v
an1568/d http://onsemi.com 8 figure 19. pspice simulated voltage levels of 5 v pecl to lvds interface with example resistor values 1.07 v 1.34 v 4.05 v 3.25 v 800 mv 270 mv lvds 5 v pecl v cm (pecl) v cm (lvds) interfacing from +3.3 v lvds to +5.0 v pecl to translate lvds signals to pecl a differential ecl device with extended common mode range inputs (see table 4) can be used to process and translate lvds signals when supplied with 5.0 v 5% supply voltage. (see figure 20) figure 20. interfacing lvds to pecl 5 v lvds z = 50 z = 50 100 pecl 3.3 v r t r t interfacing between necl to lvds on semiconductor has developed level translators to interface between the different voltage levels. the mc100ep90 translates from negative supplied ecl to lvpecl. the interface from lvpecl to lvds inputs is described above. (figure 21) figure 21. interfacing from necl to lvds necl mc100el90 or mc100ep90 lvpecl interface lvpecl to lvds lvds 3.3 v 3.3 v lvpecl ?3.3 v, ?4.5 v or ?5.2 v ?3.3 v, ?4.5 v or ?5.2 v gnd r t r t to interface from lvds to negative supplied ecl the common mode range (v ihcmr ) of the mc100lvel91 for 3.3 v supply and the mc100el91 for 4.5 v/5.2 v supply is wide enough to process lvds signals. (see figure 22) if v cc = +5 v 5% supply and a v ee = 5.2 v 5% supply is available the mc10e1651 can be used. 3.3 v figure 22. interfacing from lvds to necl lvds z = 50 z = 50 100 lvel91 or lvep91 3.3 v lvel91: ?3.3 v, el91: ?4.5 v, ?5.2 v necl gnd r t r t ?3.3 v, ?4.5 v, or ?5.2 v
an1568/d http://onsemi.com 9 notes
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